The accurate diagnosis of faults is an increasingly important aspect of testing integrated circuits, especially in view of ever-increasing gate counts and shrinking feature sizes. For circuits that do not utilize compression techniques during testing, fault diagnosis can be relatively straightforward. For circuits that have embedded compression hardware, however, accurate fault diagnosis can present a challenge.
The use of compression during the testing of integrated circuits has become widespread. In general, compression helps reduce the volume of test data required for even traditional stuck-at test sets. Such test sets, for example, often exceed the capacity of automatic test equipment (“ATE”) used to test integrated circuits. Moreover, due to the limited bandwidth between the circuit-under-test (“CUT”) and the ATE, the use of compressed test data and compressed test responses can decrease test time, and thus the test cost.
Automated fault diagnosis (e.g., diagnosis based on scan patterns obtained from automated test pattern generation (“ATPG”)) or from built-in self-test hardware, such as Logic built-in self-test (“BIST”), can be a component of an overall failure-analysis process. Automated fault diagnosis is generally used to predict the location of a failure in a CUT and has applications in such fields as silicon debugging, yield learning, and yield improvement. Given the failing test responses to a test set, an automated fault diagnosis tool desirably identifies the suspect fault sites that best explain the failures. The suspect sites identified can help locate the physical cause of the fault and can be used to guide failure analysis at the physical level.
Advances in scan diagnostics have led to diagnostics tools that are capable of identifying defect types, such as bridges or opens, as well as the potential defect location (also referred to as “fault location”) on the die. These tools are typically used to post-process uncompressed fail information that is captured after applying ATPG vectors and stored in a tester. For ATPG vectors, the tester fail information can be directly mapped to failing scan cells. For Logic BIST, conventional wisdom indicates that a single MISR signature is sufficient to identify failing devices, but does not have enough information to identify the locations of detected defects. Thus, in order to do diagnosis, one can unload exact scan cell information in a diagnostic mode and perform the same diagnosis as with regular scan ATPG.